As is well known, increased device density, together with higher speed performance and lower power consumption are major driving forces in integrated circuit manufacturing. CMOS design consideration for high speed digital applications are usually determined by the pull up time and pull down time of each individual gate. Individual gates are associated with a delay time period for signal propagation in PMOS and NMOS gate electrodes. The delay time period, in turn, is inversely proportional to the drive current (Idrive). It is therefore clear that maximizing the drive current will increase the performance speed or Figure of Merit (FOM) of a CMOS device.
Mechanical stresses are known to play a role in charge carrier mobility which affects several critical parameters including Voltage threshold (VT) shift, drive current saturation (IDsat), and ON/Off current. The effect of induced mechanical stresses to strain a MOSFET device channel region, and the effect on charge carrier mobility is believed to be influenced by complex physical processes related to acoustic and optical phonon scattering. Ideally, an increase in charge carrier mobility will also increase a drive current.
In addition, drive current is affected by gate sheet resistance. Thus the higher the sheet resistance of the gate electrode, the larger the delay time in signal propagation. Approaches in the prior art to reduce gate electrode sheet resistance have included forming silicides in an upper portion of a polysilicon gate electrode as well as forming the gate electrode of a conductive metal.
In addition, due to complex relationships between the thickness of a silicide, which remains about constant with device scaling, and scaling size reductions of the CMOS device, for example including a junction depth of source and drain regions, the problem of current leakage (diode leakage) becomes increasingly problematical at smaller device critical dimensions. Thus, prior art approaches of forming silicided gate electrodes and silicided source and drain regions increasingly leads to short channel effects including current leakage.
Conventional silicided gate electrodes of the prior art have the added liability of suffering poly-depletion effects. For example, when a gate bias is applied to the CMOS device the electrical field formed on the gate dielectric penetrates into the gate electrode causing charge carrier depletion at the electrode/gate interface which thereby decreases drive current and lowers CMOS speed performance.
These and other shortcomings demonstrate a need in the semiconductor device integrated circuit manufacturing art for improved CMOS devices and methods of manufacturing the same to achieve improved CMOS device speed performance including increased drive current.
It is therefore an object of the present invention to provide improved CMOS devices and methods of manufacturing the same to achieve improved CMOS device speed performance including increased drive current, while overcoming other shortcomings of the prior art.